Poseidon Design Systems
Triton Tuner
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The Triton Tuner is a system level design environment which enables designers to quickly analyze their architecture and modify their system for optimal performance.

Most systems consist of processors, caches, memories, buses, peripherals, function blocks, and software algorithms. It is critical for the architecture to support the efficient flow of data between the blocks to meet the performance requirements of the system. The Triton Tuner environment provides the capabilities critical to the designer for developing a robust and efficient solution. Tuner utilizes a SystemC simulation environment based on transaction level models of the system components. The hardware/software co-simulation enables the tool to collect key system performance measurements. These measurements identify the bottlenecks in the architecture which are limiting performance. Tuner provides a user-friendly interface and data visualization browser to greatly increase the efficiency of the design effort. Tuner also performs software profiling as well as the collection of system performance indices. These measurements pinpoint inefficiencies in the design and enable the concurrent optimization of the system architecture and the software. Triton Tuner models the complete memory hierarchy, which includes cache memories, write buffers, RAMs, flash memories, etc. With the key performance and utilization data available for the different components of the memory subsystem, you can quickly configure the memory subsystem to achieve maximum performance with lower power consumption.

Key Uses of Tuner

  • Increase system performance by creating an efficient memory hierarchy
  • Optimize memory hierarchy to create lower power designs
  • Tune software algorithms to run faster with less waiting on hardware
  • Reduce system optimization effort by using an effective and user friendly system analysis environment
  • Identify hot spots in algorithms through detailed profiling and reduce power by optimizing critical code
  • Identify and eliminate bottlenecks between the hardware and the software

Application profile plus memory usage data
Easily tune application code and memory hierarchy
Extensive, cache performance indices
Tune cache architecture to algorithm
Memory performance measurements
Select optimum memories size, type, speed, and configuration
Correlation between performance data and source data
Identifies problem areas between the application code and the hardware
Software profiling and performance indices
Identifies bottlenecks aiding the user in software optimization and HS/SW partitioning
User friendly data presentation and visualization
Reduction of analysis time, faster and more accurate turning decisions
Vendor certified processor models
Assure of accuracy of analysis
Co-verification environment based on SystemC transactional models
Fast simulation speeds
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